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CY7C1346F
2-Mbit (64K x 36) Pipelined Sync SRAM
Features
* Registered inputs and outputs for pipelined operation * 64K x 36 common I/O architecture * 3.3V core power supply * 3.3V I/O operation * Fast clock-to-output times -- 3.5 ns (for 166-MHz device) -- 4.0 ns (for 133-MHz device) -- 4.5 ns (for 100-MHz device) * Provide high-performance 3-1-1-1 access rate * User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous output enable * Offered in JEDEC-standard 100-pin TQFP package * "ZZ" Sleep Mode Option
Functional Description[1]
The CY7C1346F SRAM integrates 65,536 x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs. GW when active LOW causes all bytes to be written. The CY7C1346F operates from a +3.3V core power supply while all outputs also operate with a +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
Logic Block Diagram
A0, A1, A
ADDRESS REGISTER
2
A[1:0]
MODE ADV CLK
Q1
ADSC ADSP
BWD DQD,DQD BYTE WRITE REGISTER DQC,DQPC BYTE WRITE REGISTER DQB,DQPB BYTE WRITE REGISTER DQA ,DQPA BYTE WRITE REGISTER
BURST COUNTER CLR AND Q0 LOGIC
DQD ,DQPD BYTE WRITE DRIVER DQC ,DQPC BYTE WRITE DRIVER DQB,DQPB BYTE WRITE DRIVER DQA,DQPA BYTE WRITE DRIVER
BWC
MEMORY ARRAY
SENSE AMPS
OUTPUT REGISTERS
OUTPUT BUFFERS E
BWB
DQs DQPA DQPB DQPC DQPD
BWA BWE
GW CE1 CE2 CE3 OE
ENABLE REGISTER
PIPELINED ENABLE
INPUT REGISTERS
ZZ
1
SLEEP CONTROL
Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05384 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised December 3, 2004
CY7C1346F
Selection Guide
166 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 3.5 240 40 133 MHz 4.0 240 40 100 MHz 4.5 205 40 Unit ns mA mA
Pin Configuration
A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A DQPc DQc DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
BYTE C
BYTE D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100-pin TQFP CY7C1346F
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA
BYTE B
BYTE A
Document #: 38-05384 Rev. *B
MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1346F
Pin Definitions
Name A0, A1 , A TQFP 37,36,32, 33,34,35, 36,37,44, 45,46,47, 48,49,81, 82 99,100 93,94,95, 96 88 I/O Description InputAddress Inputs used to select one of the 64K address locations. Sampled Synchronous at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0 feed the 2-bit counter.
BWA, BWB BWC, BWD GW
InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Synchronous Writes to the SRAM. Sampled on the rising edge of CLK. InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising Synchronous edge of CLK, a global Write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This Synchronous signal must be asserted LOW to conduct a Byte Write. InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation.
BWE CLK
87 89
CE1 CE2 CE3 OE
98
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used Synchronous in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used Synchronous in conjunction with CE1 and CE3 to select/deselect the device. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used Synchronous in conjunction with CE1 and CE2 to select/deselect the device. InputOutput Enable, asynchronous input, active LOW. Controls the direction of Asynchronous the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. Synchronous When asserted, it automatically increments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. InputAddress Strobe from Controller, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, A is captured in the address registers. A1, A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ "Sleep" Input, active HIGH. This input, when HIGH places the device in a Asynchronous non-time-critical "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register Synchronous that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by "A" during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are placed in a three-state condition.
97 92 86
ADV ADSP
83 84
ADSC
85
ZZ
64
DQA, DQB DQC, DQD, DQPA, DQPB, DQPC,DQPD
52,53,56,57, 58,59,62,63, 68, 69,72,73, 74,75,78,79, 2,3,6,7,8,9, 12,13,18,19, 22,23,24,25, 28,29,51, 80,1,30 15,41,65, 91
VDD
Power Supply Power supply inputs to the core of the device.
Document #: 38-05384 Rev. *B
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CY7C1346F
Pin Definitions (continued)
Name VSS VDDQ TQFP 17,40,67, 90 4,11,20, 27,54,61, 70,77 5,10,21, 26,55,60, 71,76 31 I/O Ground I/O Power Supply I/O Ground Description Ground for the core of the device. Power supply for the I/O circuitry.
VSSQ
Ground for the I/O circuitry.
MODE
InputStatic
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not internally connected to the die.
NC
14,16,38, 39,42,43, 50,66
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1346F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the address register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the output registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tCO if OE is active LOW. The only exception occurs when the SRAM is emerging from a Document #: 38-05384 Rev. *B
deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the RAM array. The Write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQ inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BW[A:D] signals. The CY7C1346F provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW[A:D]) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1346F is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQ are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a Write to Page 4 of 16
CY7C1346F
the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to DQ is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because the CY7C1346F is a common I/O device, the Output Enable (OE) must be deserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQs are automatically three-stated whenever a Write cycle is detected, regardless of the state of OE.
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00
Linear Burst Address Table (MODE = GND)
First Address A1, A0 00 01 10 11 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10
Burst Sequences
The CY7C1346F provides a two-bit wraparound counter, fed by A1, A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported.
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ Active to snooze current ZZ Inactive to exit snooze current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 40 2tCYC Unit mA ns ns ns ns
Document #: 38-05384 Rev. *B
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CY7C1346F
Truth Table [2, 3, 4, 5, 6, 7]
Next Cycle Deselect Cycle, Power-down Deselect Cycle, Power-down Deselect Cycle, Power-down Deselect Cycle, Power-down Deselect Cycle, Power-down Snooze Mode, Power-down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK DQ None H X XL X L X X X L-H three-state None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current L L L L X L L L L L X X H H X H X X H H X H L X L X X H H H H H X X X X X X X X X X X X X H X H X L L L L L X X X X X X X X X X X X L L L L H L L L L L L L L L L L L L L L L L L L H H X L L H H H H H X X H X H H X X H X X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X L L L L L L H H H H H H X X X X X X X L H H H H H H L L H H H H L L X X X X X L H X L H L H L H X X L H L H X X L-H three-state L-H three-state L-H three-state L-H three-state X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H three-state Q D Q Q Q D D Q Q D D
L-H three-state
L-H three-state L-H three-state L-H three-state
L-H three-state L-H three-state
Truth Table for Read/Write[2, 3]
Function Read Read Write Byte A - (DQA and DQPA ) Write Byte B - (DQB and DQPB ) Write Bytes B, A Write Byte C - (DQC and DQPC ) Write Bytes C, A Write Bytes C, B Write Bytes C, B, A GW H H H H H H H H H BWE H L L L L L L L L BWD X H H H H H H H H BWC X H H H H L L L L BWB X H H L L H H L L BWA X H L H L H L H L
Write Byte D - (DQD and DQPD ) H L L H H H Notes: 2. X = "Don't Care." H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write Enable signals (BWA,BWB,BWC,BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA,BWB,BWC,BWD),BWE, GW = H.. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. CE1, CE2, and CE3 are available only in the TQFP package. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Three-State. OE is a don't care for the remainder of the Write cycle 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Three-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05384 Rev. *B Page 6 of 16
CY7C1346F
Truth Table for Read/Write[2, 3]
Function Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes GW H H H H H H H L BWE L L L L L L L X BWD L L L L L L L X BWC H H H L L L L X BWB H L L H H L L X BWA L H L H L H L X
Document #: 38-05384 Rev. *B
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CY7C1346F
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V DC Voltage Applied to Outputs inThree-State ...................................... -0.5V to VDDQ + 0.5V DC Input Voltage....................................-0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VDD VDDQ
3.3V -5%/+10% 3.3V -5% to VDD
Electrical Characteristics Over the Operating Range [8, 9]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[8] Input LOW Voltage[8] Input Load Current except ZZ and MODE VDDQ = 3.3V, VDD = Min., IOH = -4.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 3.3V VDDQ = 3.3V GND VI VDDQ 2.0 -0.3 -5 -30 5 -5 30 -5 5 240 225 205 100 90 80 40 Test Conditions Min. 3.135 3.135 2.4 0.4 VDD + 0.3V 0.8 5 Max. 3.6 VDD Unit V V V V V V A A A A A A mA mA mA mA mA mA mA
Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IOZ IDD Input = VSS Input = VDD Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply Current Automatic CS Power-down Current--TTL Inputs VDD = Max., IOUT = 0 mA, 6-ns cycle,166 MHz f = fMAX = 1/tCYC 7.5-ns cycle,133MHz 10-ns cycle, 100 MHz ISB1 VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC 6-ns cycle,166 MHz 7.5-ns cycle,133 MHz 10-ns cycle, 100 MHz
ISB2 ISB3
All speeds Automatic CS VDD = Max, Device Power-down Deselected, VIN 0.3V or Current--CMOS Inputs VIN > VDDQ - 0.3V, f = 0 VDD = Max, Device Automatic CS 6-ns cycle,166 MHz Power-down Deselected, or VIN 0.3V 7.5-ns cycle,133 MHz Current--CMOS Inputs or 10-ns cycle, 100 MHz VIN > VDDQ - 0.3V f = fMAX = 1/tCYC Automatic CS Power-down Current--TTL Inputs VDD = Max, Device Deselected, VIN VIH or VIN VIL, f = 0 All speeds
85 75 65 45
mA mA mA mA
ISB4
Notes: 8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 9. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05384 Rev. *B
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CY7C1346F
Thermal Resistance[10]
Parameter JA
JC
Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case)
Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51
TQFP Package 41.83 9.99
Unit C/W C/W
Capacitance[10]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V Max. Unit 5 5 5 pF pF pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 R = 317 VDDQ 5 pF GND R = 351 10% ALL INPUT PULSES 90% 90% 10% 1 ns
VL = 1.5V (a)
INCLUDING JIG AND SCOPE
1 ns
(b)
(c)
Switching Characteristics Over the Operating Range [11, 12]
166 MHz Parameter tPOWER Clock tCYC tCH tCL Output Times tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Set-up Times tAS tADS Address Set-up before CLK Rise ADSC, ADSP Set-up before CLK Rise ADV Set-up before CLK Rise 1.5 1.5 1.5 1.5 1.5 1.5 ns ns Data Output Valid after CLK Rise Data Output Hold after CLK Rise Clock to Low-Z[14, 15, 16] Clock to High-Z[14, 15, 16] OE LOW to Output Valid OE LOW to Output Low-Z[14, 15, 16] OE HIGH to Output High-Z
[14, 15, 16]
133 MHz Min. 1 7.5 3.0 3.0 Max.
100 MHz Min. 1 10 3.5 3.5 Max. Unit ms ns ns ns 4.5 2.0 0 ns ns ns 4.5 4.5 0 4.5 ns ns ns ns
Description VDD(Typical) to the First Clock Cycle Time Clock HIGH Clock LOW Access[13]
Min. 1 6.0 2.5 2.5
Max.
3.5 2.0 0 3.5 3.5 0 3.5 0 2.0 0
4.0
4.0 4.5 4.0
tADVS 1.5 1.5 1.5 ns Notes: 10. Tested initially and after any design or process change that may affect these parameters. 11. Timing reference level is 1.5V when VDDQ = 3.3V. 12. Test conditions shown in (a) of AC Test Loads unless otherwise noted. 13. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation can be initiated. 14. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 15. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 16. This parameter is sampled and not 100% tested. Document #: 38-05384 Rev. *B Page 9 of 16
CY7C1346F
Switching Characteristics Over the Operating Range (continued)[11, 12]
166 MHz Parameter tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH Address Hold after CLK Rise ADSP , ADSC Hold after CLK Rise ADV Hold after CLK Rise GW,BWE, BW[A:D] Hold after CLK Rise Data Input Hold after CLK Rise Chip Enable Hold after CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Description GW, BWE, BW[A:D] Set-up before CLK Rise Data Input Set-up before CLK Rise Chip Enable Set-Up before CLK Rise Min. 1.5 1.5 1.5 Max. 133 MHz Min. 1.5 1.5 1.5 Max. 100 MHz Min. 1.5 1.5 1.5 Max. Unit ns ns ns
Document #: 38-05384 Rev. *B
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CY7C1346F
Switching Waveforms
Read Cycle Timing[17]
t CYC
CLK
t CH t ADS t ADH
t CL
ADSP
tADS tADH
ADSC
tAS tAH
ADDRESS
A1
tWES tWEH
A2
A3 Burst continued with new base address
GW, BWE, BW[A:D]
tCES tCEH
Deselect cycle
CE
tADVS tADVH
ADV ADV suspends burst.
tOEV t OEHZ t CLZ t OELZ tCO tDOH t CHZ
OE
Data Out (Q)
High-Z
Q(A1)
t CO
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Single READ DON'T CARE UNDEFINED
BURST READ
Burst wraps around to its initial state
Note: 17. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document #: 38-05384 Rev. *B
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CY7C1346F
Switching Waveforms (continued)
Write Cycle Timing[17, 18]
t CYC
CLK tCH tADS ADSP ADSC extends burst tADS tADH tADH tCL
tADS ADSC tAS A1 tAH
tADH
ADDRESS
A2 Byte write signals are ignored for first cycle when ADSP initiates burst
A3
tWES tWEH
BWE, BW[A :D] tWES tWEH GW tCES CE t t ADVS ADVH ADV ADV suspends burst tCEH
OE tDS tDH
Data In (D)
High-Z
t OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE
DON'T CARE
UNDEFINED
Note: 18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A : D] LOW.
Document #: 38-05384 Rev. *B
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CY7C1346F
Switching Waveforms (continued)
Read/Write Cycle Timing[17, 19, 20]
tCYC
CLK tCH tADS ADSP tADH tCL
ADSC tAS tAH
ADDRESS
A1
A2
A3 tWES tWEH
A4
A5
A6
BWE, BW[A:D] tCES CE tCEH
ADV
OE tCO tDS tDH tOELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ Q(A2) Single WRITE D(A3) D(A5) D(A6)
Q(A4)
Q(A4+1) BURST READ
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
DON'T CARE
UNDEFINED
Notes: 19. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed. 20. GW is HIGH.
Document #: 38-05384 Rev. *B
Page 13 of 16
CY7C1346F
Switching Waveforms (continued)
ZZ Mode Timing[21, 22]
CLK
t ZZ t ZZREC
ZZ
t
ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Ordering Information
Speed (MHz) 166 133 100 Ordering Code CY7C1346F-166AC CY7C1346F-133AC CY7C1346F-100AC Package Name A101 A101 A101 Package Type 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack 100-lead Thin Quad Flat Pack Operating Range Commercial
Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in High-Z when exiting ZZ sleep mode.
Document #: 38-05384 Rev. *B
Page 14 of 16
CY7C1346F
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation. All product and company names mentioned in this document may be trademarks of their respective holders.
Document #: 38-05384 Rev. *B
Page 15 of 16
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1346F
Document History Page
Document Title: CY7C1346F 2-Mbit (64K x 36) Pipelined Sync SRAM Document Number: 38-05384 REV. ** *A *B ECN NO. 200661 213342 297074 Issue Date See ECN See ECN See ECN Orig. of Change NJY VBL NJY New data sheet Update Ordering Info section: add -100AC and -166AC Corrected the typo in switching characteristics for 100-MHz speed bin Description of Change
Document #: 38-05384 Rev. *B
Page 16 of 16

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